Semiconductor integrated circuits fabricated by CMOS (complementary metal-oxide-semiconductor) techniques are sensitive to an ESD event, which may be caused by contact with a human body, for example. These circuits are adversely affected by an excessively high incoming voltage (or current) from the ESD event. Such an ESD event accompanied by an excessive high voltage (or current) causes thin isolation layers of the circuits to be damaged destructively, and/or channels thereof to be shorted, often resulting in malfunctions or operational failure of integrated circuits.
ESD protection devices can be employed in integrated circuits to obviate physical damage caused by an ESD event. Such ESD protection devices are usually set between the pins of integrated circuit and inputs pads and discharge a transient voltage to the outside of an integrated circuit, in order to prevent the transient voltage from being applied to internal circuitry of the integrated circuit. Generally, the trigger voltage and holding voltage of an ESD protection device can define its performance. The lower the trigger voltage and holding voltage, the better the performance the ESD protection device can have. Thus, many designs of ESD protection devices are employed to provide lower trigger voltages and holding voltages.
An example of an ESD protection device that can be used for protection of an integrated circuit (IC) from an ESD event is a silicon-controlled rectifier (SCR). FIGS. 1A, 1B; and 1C show the basic structure of an SCR. The anode of an SCR can be connected to an IC pin, while the cathode of the SCR can be connected to a ground, for ESD protection of the IC pin. Alternatively, the anode can be connected to a power bus to prevent the IC from being damaged during an ESD event on the power bus. The SCR is triggered by n-well to p-substrate junction breakdown, which is relatively high, for instance, typically >20 V. This high breakdown voltage is a drawback when an SCR is used as an ESD protection element since it may not trigger soon enough during an ESD event to protect other circuit elements from ESD damage.
U.S. Pat. No. 5,465,189 describes an SCR used to provide on-chip protection against ESD stress applied at the input, output, power-supply bus, or between any arbitrary pair of pins of an integrated circuit. An n-type metal oxide semiconductor field effect transistor (nMOSFET) having a low breakdown voltage is incorporated into the SCR to lower the trigger voltage of the SCR. FIG. 2A shows a low-voltage trigger SCR, according to U.S. Pat. No. 5,465,189, which integrates an nMOSFET with the SCR, such that the trigger voltage of the SCR is equal to the trigger voltage of the nMOSFET, which is typically roughly at or lower than 12 volts. FIG. 2B shows a variation of FIG. 2A in which an integrated lateral bipolar device, instead of nMOSFET, is provided to reduce the trigger voltage of an SCR.